

`include "defines.v"

//----------------------------------------------------------------
//Module Name : ls_pro
//Description of module:
//process the load and store inst 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/09/13	  
//----------------------------------------------------------------

module ysyx_210195_ls_pro(
//from axi_arbi	
	input	clk,
	input	reset,
	input	ls_ready_i,
	input	[63:0]	load_data_i,	
	input	[1:0]	ls_resp,
	
	input	if_fetched,
	
	input	load_axi_en,
	input	store_axi_en,
	input	[7:0]	inst_opcode,
	
//to axi4	
	output	ls_valid_o,
	output	ls_req_o,
//	output 	[63:0]	ls_addr_o,
//	output	[63:0]	store_data_o,
	output	reg [1:0]	ls_size_o,
//to reg
	output	reg [63:0]	mem_ld_data			//->reg
//	output	reg	load_fetched	
	);

wire	ls_hs;
assign	ls_hs = ls_valid_o & ls_ready_i;
reg		ls_valid_en;
//reg		ls_fetched;
/*
always @(posedge if_fetched or posedge ls_fetched)
  begin
	else if(ls_fetched)
		ls_valid_en <= 1'b0;
	else
		ls_valid_en <= 1'b1;
  end
*/
always @(posedge clk)	begin
	if(reset)
		ls_valid_en <= 1'b0;
	else if(ls_hs)
		ls_valid_en <= 1'b0;
	else if(if_fetched)
		ls_valid_en <= 1'b1;
	else
		ls_valid_en <= ls_valid_en;

end  
assign	ls_valid_o = ls_valid_en ? (load_axi_en | store_axi_en) : 1'b0;
assign	ls_req_o = store_axi_en ? `REQ_WRITE : `REQ_READ;			//默认情况下read


always @(*)
  begin
	case(inst_opcode)
		8'b000_01000,8'b000_00000,8'b100_00000:		//sb,lb,lbu
			ls_size_o = `SIZE_B;
		8'b001_01000,8'b001_00000,8'b101_00000:		//sh,lh,lhu
			ls_size_o = `SIZE_H;
		8'b010_01000,8'b010_00000,8'b110_00000:		//sw,lw,lwu
			ls_size_o = `SIZE_W;
		8'b011_01000,8'b011_00000:		//sd,ld
			ls_size_o = `SIZE_D;
		default:
			ls_size_o = 2'b00;
	endcase
  end

always @(posedge clk)
  begin
	if(reset)	begin
//		load_fetched <= 1'b0;
//		ls_fetched <= 1'b0;
		mem_ld_data <= 64'd0;
	end
	else if(ls_hs)	begin
//		load_fetched <= load_axi_en ? 1'b1 : 1'b0;
//		ls_fetched <= 1'b1;
		mem_ld_data <= (inst_opcode == 8'b000_00000) ? {{56{load_data_i[7]}},load_data_i[7:0]} : 	//lb
					(inst_opcode == 8'b100_00000) ? {{56{1'b0}},load_data_i[7:0]} :			//lbu
					(inst_opcode == 8'b001_00000) ? {{48{load_data_i[15]}},load_data_i[15:0]} : 	//lh
					(inst_opcode == 8'b101_00000) ? {{48{1'b0}},load_data_i[15:0]} : 		//lhu
					(inst_opcode == 8'b010_00000) ? {{32{load_data_i[31]}},load_data_i[31:0]} : 	//lw
					(inst_opcode == 8'b110_00000) ? {{32{1'b0}},load_data_i[31:0]} :		//lwu
					(inst_opcode == 8'b011_00000) ? load_data_i : 64'd0;					//ld
	end
//	else	begin
//		load_fetched <= 1'b0;
//		ls_fetched <= 1'b0;
		
//	end
  end


endmodule
